This invention relates to a technique for fabrication of a semiconductor integrated circuit device and the semiconductor integrated circuit device fabricated by using this technique. Particularly, the present invention pertains to a technique which is effective when applied to a semiconductor integrated circuit device having a metal interconnection, which has, as a main conductive film, copper or the like, and is formed by depositing a thin copper film in a groove and removing a portion of the thin copper film from a region outside the groove by the CMP (Chemical Mechanical Polishing) method.
In the conventional semiconductor integrated circuit device, an interconnection film was formed, for example, by forming a thin film of a high-melting-point metal, such as aluminum (Al) alloy or tungsten (W), over an insulating film, forming a resist pattern having the same shape as that of the interconnection pattern over a thin film for interconnection by photolithography and then forming the interconnection pattern by dry etching using the resist pattern as a mask.
The conventional process using an Al alloy or the like is, however-accompanied with a drawback in that, attendant on the miniaturization of the interconnection, the interconnection resistance shows a marked increase, which inevitably increases an interconnection delay, resulting in a deterioration in the performance of the semiconductor integrated circuit device. Such a drawback has led to a serious problem particularly in a high-performance logic LSI and represents a factor for disturbing its performance.
The IBM J. Res. Develop., 39(4), the July issue, 419-435(1995) or 1996 Symposium on VLSI Technology Digest of Technical Papers, pp48-49, describes a process (so-called damascene method) for forming an interconnection pattern in a groove, which comprises embedding an interconnection metal, which has copper (Cu) as a main conductive film, formed in an insulating film and then removing an unnecessary portion of the metal outside the groove by the CMP (chemical machine polishing) method.
The Japanese Patent Application Laid-Open No. HEI 7-297183, describes a technique which comprises forming an interconnection groove on an insulating film formed over a semiconductor substrate, overlaying another insulating film, overlaying a conductive interconnection film, forming a planarizing film made of SOG (Spin On Glass) so as to embed the interconnection groove with the planarizing film, and polishing the planarizing film. The conductive interconnection film, thereby leaving an interconnection made of the conductive interconnection film in the interconnection groove.
As a result of investigation on the above process which comprises embedding an interconnection metal having copper (Cu) or the like as a main conductor film in a groove formed in an insulating film and then removing an unnecessary portion of the metal outside the groove by the CMP (Chemical Mechanical Polishing) method, however, the present inventors found that the process is accompanied with the following problems. The problems investigated by the present inventors will be described with reference to FIG. 73(a) to 73(c), in which FIG. 73(a) is a plain view, FIG. 73(b) is a cross-sectional view taken along a line bxe2x80x94b of FIG. FIG. 73(a) and FIG. 73(c) is a cross-sectional view taken along a line cxe2x80x94c of FIG. FIG. 73(a), and wherein only a problematic interconnection film is illustrated while other members are omitted.
For the formation of an interconnection 202 over an insulating film 201, first, an insulating film 203 for interconnection formation is deposited over the insulating film 201 and an interconnection groove 204 is formed in the insulating film 203. As the insulating film 203, a silicon oxide film is usually employed. Second, a metal film (for example, copper (Cu)) which is to constitute the interconnection 202 is deposited over the insulating film 203 so as to embed the interconnection groove 204, followed by the removal of a portion of the metal film over the insulating film 203 outside the interconnection groove 204 by polishing, whereby only the metal film inside the interconnection groove 204 remains and the interconnection 202 is formed. When the silicon oxide film used as the insulating film 203 is compared with the metal (ex. copper) which constitutes the interconnection film 202, the polishing rate of the latter by the CMP method is generally greater. Such a difference in the polishing rate inevitably results in a concave portion 205 being formed on the surface of the interconnection 202. This concave portion 205 is known as dishing (concave). In addition, scratches appear on the surface of the insulating film 203 as a result of polishing by the CMP method.
If an insulating film 206 is formed over such a concave portion 205 or a scratch without removing it from the surface of the insulating film 203, another concave portion 205 or a further concave portion attributable to the scratch also appears on the surface of the insulating film 206. If a plug 207 is formed in the insulating film 206 by the CMP method without removing the concave portion, the conductive substance 208 which constitutes the plug 207 remains in the concave portion on the surface of the insulating film 206. Described more specifically, the plug 207 is formed by embedding a metal film, which is to constitute the plug 207, inside a connecting hole opened in the insulating film 206 and, at the same time, depositing the metal film over the insulating film 206; and then removing the metal film over the insulating film 206 by the CMP method to leave only a portion-of the metal film inside of the connecting hole. If a concave portion (including a concave portion attributable to a scratch) exists on the surface of the insulating film 206, the conductive substance 208, which is a residue of the metal film, also remains inside of the concave portion. Incidentally, there is a possibility of that the metal film will remain in the concave portion attributable to a scratch, but this is not illustrated.
Such a residue of the conductive substance 208 is not intended and is undesired, because when an insulating film 209 is formed over the plug 207 and an interconnection 210 is formed in the interconnection groove of the insulating film 209, two adjacent interconnections 210, which are to be electrically disconnected, form a short circuit owing to the existence of the conductive substance 208, leading to a short-circuit problem in the semiconductor integrated circuit device.
Such a short circuit problem occurs similarly when an interconnection is formed by the so-called dual damascene method without using the plug 207.
An object of the present invention is to provide a technique for improving surface flatness of an interlayer insulating film over a first metal interconnection formed by the CMP method.
Another object of the present invention is to suppress a short circuit of a second metal interconnection over a first metal interconnection formed by the CMP method, thereby improving the yield and reliability of the semiconductor integrated circuit device.
The above-described and other objects and novel features of the present invention will be apparent from the description herein and the drawings attached.
Among the aspects of the inventions disclosed herein, representative ones will next be summarized simply.
(1) In one aspect of the present invention, there is provided a semiconductor integrated circuit device which comprises a semiconductor device formed over a principal surface of a semiconductor substrate; a first insulating film which is formed over the semiconductor device and has a first conductive member, which has been formed by the CMP method, embedded in each of first concave portions formed in the first insulating film; and a second insulating film which is formed over the first insulating film and has a second conductive member, which has been formed by the CMP method, embedded in each of second concave portions formed in the second. insulating film, the second insulating film including a fluid insulating film having self fluidity.
According to such a semiconductor integrated circuit device, even if dishing (concave) appears in the first conductive member, which has been embedded in the first insulating film, as a result of polishing by the CMP method or the first insulating film has a scratch on its surface as a result of polishing by the CMP method, the surface is planarized because the second insulating film includes a fluid insulating film, and influence of the above dishing or scratch is not observed from the surface of the second insulating film, whereby a conductive member to be embedded in the second insulating film is formed evenly by the CMP method. In other words, if the fluid insulating film is not formed, the second conductive member to be embedded in the second insulating film does not remain in the concave portion on the surface of the second insulating film, whereby a short circuit between two adjacent conductive members of the second insulating film, which otherwise occurs due to the residue, can be prevented. Consequently, the yield and reliability of the semiconductor integrated circuit can be improved.
When a concave portion exists on the surface of the second insulating film, it becomes necessary to excessively polish a portion of the second insulating film for the formation of the second conductive member. In the present invention, since such a concave portion is not formed on the surface of the second insulating film, excessive polishing is not required. As a result, a short circuit can be avoided by preventing dishing of the second conductive member embedded in the second insulating film and evenly forming the conductive member to be overlaid for reasons similar to the above described ones.
Incidentally, it is possible to form the first or second insulating film as an interconnection-forming insulating film which has an interconnection formed in its concave portion or an interconnection interlayer insulating film which insulates between interconnection films; to form the concave portion as an interconnection groove formed in the interconnection-forming insulating film or a connecting groove formed in the interconnection interlayer insulating film; and to form a conductive member as an interconnection formed in the interconnection groove or a plug formed in the connecting hole.
In addition, it is possible to form the fluid insulating film to be included only in the interconnection interlayer insulating film positioned on the interconnection formed in the interconnection groove of the interconnection-forming insulating film; to be contained only in the interconnection-forming insulating film positioned on the plug formed in the connecting hole of the interconnection interlayer insulating film; or to be contained in both the interconnection interlayer insulating film positioned on the interconnection formed in the interconnection groove of the interconnection-forming insulating film and the interconnection-forming insulating film positioned on the plug formed in the connecting hole of the interconnection interlayer insulating film.
The concave portion may be made of an interconnection groove formed in the vicinity of the surfaces of the first and second insulating films and a connecting hole formed below the interconnection groove, and in the conductive member, an interconnection portion formed in the interconnection groove may be integrally formed with a connecting portion formed in the connecting hole. In other words, the present invention can also be applied to an interconnection (interconnection by the so-called dual damascene method) wherein a connecting hole portion and an interconnection groove portion have been integrally formed.
The second insulating film, interconnection interlayer insulating film and interconnection-forming insulating film each containing a fluid insulating film may have a three-layer structure of a non-fluid insulating film having no self fluidity, a fluid insulating film and a non-fluid insulating film.
As the fluid insulating film, an SOG film can be used. Examples of the SOG film include organic SOG films, inorganic SOG films and polysilazane SOG films. Among them, inorganic SOG films are particularly preferred. If an organic SOG film is used as the fluid insulating film, the shrinkage or heightening of water absorption of the organic SOG film occurs upon processing of the second insulating film, interconnection interlayer insulating film or interconnection-forming insulating film which contains the organic SOG film by photolithography and by removing the photoresist film, that is, a mask for photolithography by oxygen ashing, which adversely affects the reliability of the semiconductor integrated circuit device. The use of the inorganic SOG film as a fluid insulating film, however, does not cause such an inconvenience.
As the fluid insulating film, it is possible to use a silicon oxide film prepared by forming a silanol in a gaseous phase and then reacting the resulting silanol on a low-temperature substrate.
The SOG film is formed by application in an air In atmosphere. A silicon oxide film formed by silanol formation in a gaseous phase and the reaction of the silanol on the low-temperature substrate, more specifically, formed by allowing silanol (HnSi(OH)4xe2x88x92n), which has been prepared by the combination of a silane gas (SiH4) and hydrogen peroxide (H2O2) under reduced pressure, to absorb to the surface of a substrate to form a film, can also be given as an example of the fluid insulating film. Here, a silane gas is exemplified as a raw material gas for the formation of a silanol, but methylsilane (dimethylsilane, trimethylsilane or the like) or ethylsilane (diethylsilane, triethylsilane or the like) having, as a substituent for a hydrogen group (xe2x80x94H), an alkyl group such as methyl (xe2x80x94CH3) or ethyl (xe2x80x94C2H5) may be used.
The width W of each of the concave portion, interconnection groove and connecting hole may fall within a range of from its minimum width Wmix to the maximum width Wmx and satisfy the condition of Wmaxxe2x89xa64xc3x97Wmin.
(2) In another aspect of the present invention, there is also provided a semiconductor integrated circuit device which comprises a semiconductor device formed on a principal surface of a semiconductor substrate; a first insulating film which is formed over the semiconductor device and has a first conductive member, which has been formed by the CMP method, embedded in each of first concave portions formed in the first insulating film; and a second insulating film which is formed over the first insulating film and has a second conductive member, which has been formed by the CMP method, embedded in each of second concave portions formed in the second insulating film, the second insulating film including an insulating film planarized by the CMP method.
According to such a semiconductor integrated circuit device, the second insulating film is able to have a planarized surface owing to the insulating film planarized by the CMP method as described above in (1) and the second conductive member to be embedded in the second insulating film is therefore formed securely, whereby occurrence of a short circuit can be prevented By preventing excessive polishing of the second conductive member embedded in the second insulating film, thereby overlaying another conductive member securely, occurrence of a short circuit can be prevented, which, similar to (1), makes it possible to improve the yield and reliability of the semiconductor integrated circuit device.
The semiconductor integrated circuit devices as described above in (1) and (2) each may have, over the interconnection formed in its concave portion or interconnection groove, a diffusion preventive film for preventing the diffusion of metal elements which constitute the interconnection, for example, a silicon nitride film formed by the plasma CVD method. The existence of such a diffusion preventive film makes it possible to secure the withstand voltage of the interconnection interlayer insulating film, thereby improving the reliability of the semiconductor integrated circuit device.
(3) In a further aspect of the present invention, there is also provided a process for the fabrication of a semiconductor integrated circuit device which comprises a semiconductor device formed on the principal surface of a semiconductor substrate, a first insulating film which has been formed over the semiconductor device and has a first conductive member embedded in one portion of the first insulating film and a second insulating film which has been formed over the first insulating film and has a second conductive member embedded in one portion of the second insulating film. It comprises (a) depositing the first insulating film over the semiconductor substrate having at least the semiconductor device formed thereon and forming first concave portions in the first insulating film; (b) forming, on the surface of the first insulating film including the inside surface of the first concave portions, a first conductive film to be embedded in the first concave portions, (c) polishing the first conductive film by the CMP method to leave only a portion of the first conductive film inside of each of the first concave portions of the first insulating film, thereby forming the first conductive member, (d) depositing over the first conductive member a fluid insulating film having self fluidity and (e) forming second concave portions in the second insulating film including the fluid insulating film, forming a second conductive film to be embedded in each of the second concave portions and then polishing the second conductive film by the CMP method, thereby forming the second conductive member.
According to the above process, the semiconductor integrated circuit device as described above in (1) can be fabricated.
Incidentally, when the fluid insulating film is an SOG film, the SOG film is applied onto the semiconductor substrate, followed by thermal treatment.
When the fluid insulating film is a silicon oxide film formed by the formation of a silanol in a gaseous phase and reaction of the resulting silanol on a low-temperature substrate, it can be formed by retaining the semiconductor substrate at a low temperature not higher than 100xc2x0 C. in a reaction chamber under reduced pressure, introducing SiHxM4xe2x88x92x (wherein M represents a C1-3 alkyl group, 1xe2x89xa6xc3x97xe2x89xa64) and H2O2 into the reaction chamber to prepare a silanol and then heat treating the semiconductor substrate having the silanol deposited thereon. In this case, the larger the number of carbon atoms of the alkyl group (xe2x80x94M), the lower the vapor pressure becomes. The wall surface temperature of the reaction chamber can hence be heightened and the temperature of the semiconductor substrate can be reduced to the minimum, which makes it possible to accelerate the adsorption of an alkylsilane (SiHxM4xe2x88x92x) on the semiconductor substrate maintained at low temperature, thereby increasing the possibility of the silanol formation reaction occurring in the vicinity of the surface of the semiconductor substrate. As a result, the yield of the raw material gas can be increased. Incidentally, the raw material gas is preferably supplied in a gaseous phase so that alkyl groups having not more than 3 carbon atoms are preferred.
The width W of each of the first concave portions which will have the first conductive member formed therein can be formed so that the maximum width Wmax is within a range of four times as much as the minimum width Wmin (Wmin xe2x89xa6Wxe2x89xa64xc3x97Wmin).
In the conductive film embedded in each of the first concave portions of the first insulating film in the above step (b), its height H1 in the concave portion of the minimum width Wmin may be almost equal to the height H2 in the concave portion of the maximum width Wmax (H1≅H2) and the heights H1 and H2 can be made higher than the height L1 of the surface of the first insulating film (H1≅H2 greater than L2).
According to such a process for the fabrication of a semiconductor integrated circuit device, the first conductive member formed in the step (b) is embedded in all of the first concave portions of the first insulating film and the surface of the first conductive member itself is polished and planarized. In this point, the present invention differs from the technique described in Japanese Patent Application Laid-Open No. HEI 7-297183. In the known technique, the surface height of a conductive film is lower than that of an interconnection groove in a wider interconnection groove so that when the conductive film is covered with a film such as SOG, followed by polishing to form an interconnection in the interconnection groove, the SOG film remains in the concave portion on the interconnection surface. In the present invention, on the other hand, a fluid insulating film such as SOG is deposited subsequent to the polishing for the formation of a first conductive member and the invention process therefore differs from the above technique in the order of steps. in addition, as described above, a height H1 of the concave portion of the minimum width Wmin is substantially similar to a height H2 of the concave portion of the maximum width Wmax (H1≅H2) and, at the same time, the heights H1 and H2 are both higher than a height L1 of the first insulating film (H1=H2 greater than L1) so that the invention process differs from the above technique in the formation step itself for forming the first conductive member (corresponding to the interconnection in the above technique). The semiconductor integrated circuit devices fabricated by these two different processes are inevitably different and in the semiconductor integrated circuit device fabricated according to the present invention, a fluid insulating film such as SOG does not remain even if a concave portion (dishing) is formed on the first conductive member by the CMP method.
In the first conductive member polished in the above step (c), the dishing amount K1 on the surface of the first conductive member in the concave portion of the minimum width Wmin and the dishing amount K2 on the surface of the first conductive member in the concave portion of the maximum width Wmax are substantially the same (K1≅K2). Such a fabrication process of a semiconductor integrated circuit device is available based on the above-described condition of H1≅H2.
It is also possible to form a second insulating film by depositing a CVD silicon oxide film by the plasma CVD method or thermal CVD method prior to the deposition of the fluid insulating film, depositing the fluid insulating film and then depositing thereover a CVD oxide film.
After the formation of the first conductive member, a diffusion preventive film, for example, a silicon nitride film, which covers the surface of the first conductive member can be deposited thereon.
By such a fabrication process, it is possible to prevent the diffusion of a metal element such as copper which constitutes the first conductive member, thereby improving the reliability of the semiconductor integrated circuit.
(4) In a still further aspect of the present invention, there is also provided a process for the fabrication of a semiconductor integrated circuit device which has a semiconductor device formed on the principal surface of a semiconductor substrate, a first insulating film which has been formed over the semiconductor device and has a first conductive member partially embedded therein and a second insulating film which has been formed over the first insulating film and has a second conductive member partially embedded therein; which comprises (a) depositing the first insulating film on the semiconductor substrate having at least the semiconductor device formed thereon and forming first concave portions in one portion of the first insulating film; (b) forming over the surface of the first insulating film including the inside surface of each of the first concave portions a first conductive film to be embedded in each of the first concave portions; (c) polishing the first conductive film by the CMP method to leave a portion of the first conductive film inside of each of the first concave portions of the first insulating film, thereby forming the first conductive member; (d) depositing a silicon oxide film over the first conductive member and polishing the silicon oxide film by the CMP method for planarization; and (e) forming second concave portions in the second insulating film including the silicon oxide film, forming a conductive film to be embedded in each of the second concave portions and polishing the conductive film by the CMP method, thereby forming a second conductive member.
According to the above-described fabrication process, a semiconductor integrated circuit device as described above in (2) can be fabricated. Incidentally, the silicon oxide film included in the second insulating film is planarized by the CMP method so that it is not required to have self fluidity and may be a silicon oxide film formed by the plasma CVD method or the CVD method using TEOS (tetramethoxysilane) or the like.